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authorPeter Maydell <peter.maydell@linaro.org>2024-03-20 12:01:32 +0000
committerPeter Maydell <peter.maydell@linaro.org>2024-03-20 12:01:32 +0000
commitbc36f12e64bacf85d284c256d9de34319ef475a0 (patch)
tree49d4629ba486a340df3da35c01e131bc8460a740 /target/hppa/mem_helper.c
parent9051995517e1eab4851bfe85d3d43f2d426d18ed (diff)
parent518d2f4300e5c50a3e6416fd46e58373781a5267 (diff)
Merge tag 'pull-pa-20240319' of https://gitlab.com/rth7680/qemu into staging
target/hppa: Fix load/store offset assembly for wide mode target/hppa: Fix LDCW,S shift target/hppa: Fix SHRPD conditions target/hppa: Fix access_id checks target/hppa: Exit TB after Flush Instruction Cache target/hppa: Fix MFIA result target hppa: Fix STDBY,E # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmX6LjYdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8uoAgAtEGgWqZNRNa/neD7 # 0Dix2sTz85hqob2/4ajmEhy5XlF8V+5gCz15vHDCr+J0VIbAZj90HAolhplViBn2 # twwEbf8CjJ7g/rDF2L2rwCv4cG72yKyMWTTXXCQGuzo977ObfRgmguCsFSoRlkdD # YuiAUEt/jziGmv4wYv/9zymQUEydeMGFnmCgIwRxg6IT4krI7C5g8198wA0Eu59Y # SZMWquzKv3+gezETHs/PSco4ZM5EeoKzsIWA+hhUP/hbBdEW4w+AtPB2ZSlywluX # ALU97bZRgncCAeNENgTNoVQ8WTg1p5t3opP4vQR2afzhqLkMPMX4RCo8BaHhDzmm # srvqpw== # =DpgT # -----END PGP SIGNATURE----- # gpg: Signature made Wed 20 Mar 2024 00:30:46 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-pa-20240319' of https://gitlab.com/rth7680/qemu: target/hppa: fix do_stdby_e() target/hppa: mask privilege bits in mfia target/hppa: exit tb on flush cache instructions target/hppa: fix access_id check target/hppa: fix shrp for wide mode target/hppa: ldcw,s uses static shift of 3 target/hppa: Fix assemble_12a insns for wide mode target/hppa: Fix assemble_11a insns for wide mode target/hppa: Fix assemble_16 insns for wide mode Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/hppa/mem_helper.c')
-rw-r--r--target/hppa/mem_helper.c78
1 files changed, 61 insertions, 17 deletions
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 80f51e753f..84785b5a5c 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -152,6 +152,49 @@ static HPPATLBEntry *hppa_alloc_tlb_ent(CPUHPPAState *env)
return ent;
}
+#define ACCESS_ID_MASK 0xffff
+
+/* Return the set of protections allowed by a PID match. */
+static int match_prot_id_1(uint32_t access_id, uint32_t prot_id)
+{
+ if (((access_id ^ (prot_id >> 1)) & ACCESS_ID_MASK) == 0) {
+ return (prot_id & 1
+ ? PAGE_EXEC | PAGE_READ
+ : PAGE_EXEC | PAGE_READ | PAGE_WRITE);
+ }
+ return 0;
+}
+
+static int match_prot_id32(CPUHPPAState *env, uint32_t access_id)
+{
+ int r, i;
+
+ for (i = CR_PID1; i <= CR_PID4; ++i) {
+ r = match_prot_id_1(access_id, env->cr[i]);
+ if (r) {
+ return r;
+ }
+ }
+ return 0;
+}
+
+static int match_prot_id64(CPUHPPAState *env, uint32_t access_id)
+{
+ int r, i;
+
+ for (i = CR_PID1; i <= CR_PID4; ++i) {
+ r = match_prot_id_1(access_id, env->cr[i]);
+ if (r) {
+ return r;
+ }
+ r = match_prot_id_1(access_id, env->cr[i] >> 32);
+ if (r) {
+ return r;
+ }
+ }
+ return 0;
+}
+
int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
int type, hwaddr *pphys, int *pprot,
HPPATLBEntry **tlb_entry)
@@ -224,29 +267,30 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
break;
}
+ /*
+ * No guest access type indicates a non-architectural access from
+ * within QEMU. Bypass checks for access, D, B, P and T bits.
+ */
+ if (type == 0) {
+ goto egress;
+ }
+
/* access_id == 0 means public page and no check is performed */
if (ent->access_id && MMU_IDX_TO_P(mmu_idx)) {
- /* If bits [31:1] match, and bit 0 is set, suppress write. */
- int match = ent->access_id * 2 + 1;
-
- if (match == env->cr[CR_PID1] || match == env->cr[CR_PID2] ||
- match == env->cr[CR_PID3] || match == env->cr[CR_PID4]) {
- prot &= PAGE_READ | PAGE_EXEC;
- if (type == PAGE_WRITE) {
- ret = EXCP_DMPI;
- goto egress;
- }
+ int access_prot = (hppa_is_pa20(env)
+ ? match_prot_id64(env, ent->access_id)
+ : match_prot_id32(env, ent->access_id));
+ if (unlikely(!(type & access_prot))) {
+ /* Not allowed -- Inst/Data Memory Protection Id Fault. */
+ ret = type & PAGE_EXEC ? EXCP_IMP : EXCP_DMPI;
+ goto egress;
}
- }
-
- /* No guest access type indicates a non-architectural access from
- within QEMU. Bypass checks for access, D, B and T bits. */
- if (type == 0) {
- goto egress;
+ /* Otherwise exclude permissions not allowed (i.e WD). */
+ prot &= access_prot;
}
if (unlikely(!(prot & type))) {
- /* The access isn't allowed -- Inst/Data Memory Protection Fault. */
+ /* Not allowed -- Inst/Data Memory Access Rights Fault. */
ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR;
goto egress;
}