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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-05-24 16:20:18 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-05-28 14:29:01 +0100 |
| commit | fe84877ed44040dc128362b61dbfd923b851d6ef (patch) | |
| tree | 357f04457b27d92ae473912d618303c42698ca85 /target/arm | |
| parent | db36e14501e8745a6e23f611f917d40a27cc5dee (diff) | |
target/arm: Zero-extend writeback for fp16 FCVTZS (scalar, integer)
Fixes RISU mismatch for "fcvtzs h31, h0, #14".
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/tcg/translate-a64.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4126aaa27e..d97acdbaf9 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -8707,6 +8707,9 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, read_vec_element_i32(s, tcg_op, rn, pass, size); fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); if (is_scalar) { + if (size == MO_16 && !is_u) { + tcg_gen_ext16u_i32(tcg_op, tcg_op); + } write_fp_sreg(s, rd, tcg_op); } else { write_vec_element_i32(s, tcg_op, rd, pass, size); |