diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-14 16:09:12 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-16 14:33:52 +0100 |
| commit | c485ce2c491a6e5d66da1d1555ecd474b450db98 (patch) | |
| tree | bbc6385c6f24969eb9d7d0c2c53adae7b3e63dbf /target/arm/vfp_helper.c | |
| parent | 6e802db3c418e522b25a16fd74ea6d98fc2a1480 (diff) | |
target/arm: Enable FPSCR.QC bit for MVE
MVE has an FPSCR.QC bit similar to the A-profile Neon one; when MVE
is implemented make the bit writeable, both in the generic "load and
store FPSCR" helper functions and in the code for handling the NZCVQC
sysreg which we had previously left as "TODO when we implement MVE".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-3-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/vfp_helper.c')
| -rw-r--r-- | target/arm/vfp_helper.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 496f003477..8a71660059 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -220,7 +220,8 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) FPCR_LTPSIZE_LENGTH); } - if (arm_feature(env, ARM_FEATURE_NEON)) { + if (arm_feature(env, ARM_FEATURE_NEON) || + cpu_isar_feature(aa32_mve, cpu)) { /* * The bit we set within fpscr_q is arbitrary; the register as a * whole being zero/non-zero is what counts. |