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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-07 14:04:26 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-07 14:04:26 +0000 |
| commit | cc28fc30e333dc2f20ebfde54444697e26cd8f6d (patch) | |
| tree | 39918d91457e028c2b142294678c5e9d309a4825 /target/arm/translate.h | |
| parent | a7469a3c1edc7687d7d25967bc2c0280de202bca (diff) | |
target/arm: Update get_a64_user_mem_index for VHE
The EL2&0 translation regime is affected by Load Register (unpriv).
The code structure used here will facilitate later changes in this
area for implementing UAO and NV.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.h')
| -rw-r--r-- | target/arm/translate.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h index a32b6b1b3a..5b167c416a 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -73,6 +73,8 @@ typedef struct DisasContext { * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. */ bool is_ldex; + /* True if AccType_UNPRIV should be used for LDTR et al */ + bool unpriv; /* True if v8.3-PAuth is active. */ bool pauth_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ |