diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2019-08-15 09:46:43 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-08-16 14:02:49 +0100 |
| commit | 43722a6d4f0c92f7e7e1e291580039b0f9789df1 (patch) | |
| tree | 1979c88a7b886badac9e5d875d6e625c94ad9320 /target/arm/translate-a64.h | |
| parent | 331b1ca616cb708db30dab68e3262d286e687f24 (diff) | |
target/arm: Introduce pc_curr
Add a new field to retain the address of the instruction currently
being translated. The 32-bit uses are all within subroutines used
by a32 and t32. This will become less obvious when t16 support is
merged with a32+t32, and having a clear definition will help.
Convert aarch64 as well for consistency. Note that there is one
instance of a pre-assert fprintf that used the wrong value for the
address of the current instruction.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190807045335.1361-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.h')
| -rw-r--r-- | target/arm/translate-a64.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 9ab40872d8..9cd2b3d238 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -25,7 +25,7 @@ void unallocated_encoding(DisasContext *s); qemu_log_mask(LOG_UNIMP, \ "%s:%d: unsupported instruction encoding 0x%08x " \ "at pc=%016" PRIx64 "\n", \ - __FILE__, __LINE__, insn, s->pc - 4); \ + __FILE__, __LINE__, insn, s->pc_curr); \ unallocated_encoding(s); \ } while (0) |