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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-06-28 15:23:43 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-07-11 11:41:33 +0100 |
| commit | 81ae37dbb4a5c5b8eb54bc7f5e6c69097eacb9d2 (patch) | |
| tree | 5045f728b3b6c80c98e426c00ecd4f63509a19e7 /target/arm/tcg | |
| parent | abf1046a155bc73ceb2c3be3fdfb9c8ffebf9dd1 (diff) | |
target/arm: Implement store_cpu_field_low32() macro
We already have a load_cpu_field_low32() to load the low half of a
64-bit CPU struct field to a TCGv_i32; however we haven't yet needed
the store equivalent. We'll want that in the next patch, so
implement it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240628142347.1283015-6-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/tcg')
| -rw-r--r-- | target/arm/tcg/translate-a32.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h index 19de6e0a1a..0b1fa57965 100644 --- a/target/arm/tcg/translate-a32.h +++ b/target/arm/tcg/translate-a32.h @@ -83,6 +83,13 @@ void store_cpu_offset(TCGv_i32 var, int offset, int size); sizeof_field(CPUARMState, name)); \ }) +/* Store to the low half of a 64-bit field from a TCGv_i32 */ +#define store_cpu_field_low32(val, name) \ + ({ \ + QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 8); \ + store_cpu_offset(val, offsetoflow32(CPUARMState, name), 4); \ + }) + #define store_cpu_field_constant(val, name) \ store_cpu_field(tcg_constant_i32(val), name) |