diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-06-16 10:32:25 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-06-16 10:32:25 +0100 |
| commit | 0fa1ab0302badabc3581aefcbb2f189ef52c4985 (patch) | |
| tree | e3e676235948f172b5ce44d20ceccc697b37335f /target/arm/neon-dp.decode | |
| parent | b28be09570d0827969b62b8f82b0f720a9915427 (diff) | |
target/arm: Convert Neon 3-reg-diff narrowing ops to decodetree
Convert the narrow-to-high-half insns VADDHN, VSUBHN, VRADDHN,
VRSUBHN in the Neon 3-registers-different-lengths group to
decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/neon-dp.decode')
| -rw-r--r-- | target/arm/neon-dp.decode | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode index 144a527ee6..a2234dfa4f 100644 --- a/target/arm/neon-dp.decode +++ b/target/arm/neon-dp.decode @@ -438,5 +438,11 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm VSUBW_S_3d 1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff VSUBW_U_3d 1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff + + VADDHN_3d 1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff + VRADDHN_3d 1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff + + VSUBHN_3d 1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff + VRSUBHN_3d 1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff ] } |