diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2022-04-01 17:16:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-01 17:16:48 +0100 |
| commit | ea72ac9bc8fcb90405768412ebb9ff01d3b1a2bb (patch) | |
| tree | ff66a61c4496f029974860f62ab50e56921d1fdc /target/arm/internals.h | |
| parent | 697d18b1bd2667efa418cc7d7248d5450da547e7 (diff) | |
| parent | a5b1e1ab662aa6dc42d5a913080fccbb8bf82e9b (diff) | |
Merge tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* target/arm: Fix some bugs in secure EL2 handling
* target/arm: Fix assert when !HAVE_CMPXCHG128
* MAINTAINERS: change Fred Konrad's email address
# gpg: Signature made Fri 01 Apr 2022 15:59:59 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen
MAINTAINERS: change Fred Konrad's email address
target/arm: Determine final stage 2 output PA space based on original IPA
target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk
target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
target/arm: Fix MTE access checks for disabled SEL2
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
| -rw-r--r-- | target/arm/internals.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h index a34be2e459..7f696cd36a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1094,7 +1094,7 @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, && !(env->cp15.scr_el3 & SCR_ATA)) { return false; } - if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + if (el < 2 && arm_is_el2_enabled(env)) { uint64_t hcr = arm_hcr_el2_eff(env); if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { return false; |