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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-03-30 16:37:15 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-03-30 16:37:15 +0100 |
| commit | b471d5549188d01730131a322c4d154585ba1e60 (patch) | |
| tree | a591d8f004ac1a80c9dff7eab34dae81df6454b9 /target/arm/cpu64.c | |
| parent | 4a0ba67c77a425436e867fcbb8c513b44d7e7d6e (diff) | |
| parent | b9e3f1579a4b06fc63dfa8cdb68df1c58eeb0cf1 (diff) | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210330' into staging
* net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set
* hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
* hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
* target/arm: Make number of counters in PMCR follow the CPU
* hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
# gpg: Signature made Tue 30 Mar 2021 14:23:33 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210330:
hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
target/arm: Make number of counters in PMCR follow the CPU
hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu64.c')
| -rw-r--r-- | target/arm/cpu64.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0a9e968c9..5d9d56a33c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -141,6 +141,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; + cpu->isar.reset_pmcr_el0 = 0x41013000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } @@ -194,6 +195,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; + cpu->isar.reset_pmcr_el0 = 0x41033000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } @@ -245,6 +247,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; + cpu->isar.reset_pmcr_el0 = 0x41023000; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } |