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authorMax Filippov <jcmvbkbc@gmail.com>2011-10-10 06:25:40 +0400
committerBlue Swirl <blauwirbel@gmail.com>2011-10-15 21:03:40 +0000
commit6825b6c33c5668f0993b03937623d3e891aa540f (patch)
tree27768a91cf985bf2e43d0521bc9e2b96e0f685c5 /target-xtensa/cpu.h
parent890c6333b28a4dcbf2a26a5a17b0e71304d5a851 (diff)
target-xtensa: implement MAC16 option
See ISA, 4.3.7 for the details. - add ACC and MR special registers; - implement MAC16 and all inner MAC* opcode groups. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/cpu.h')
-rw-r--r--target-xtensa/cpu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 966f515249..b43e565254 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -113,6 +113,9 @@ enum {
BR = 4,
LITBASE = 5,
SCOMPARE1 = 12,
+ ACCLO = 16,
+ ACCHI = 17,
+ MR = 32,
WINDOW_BASE = 72,
WINDOW_START = 73,
PTEVADDR = 83,