diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-04-20 08:56:19 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-04-26 23:02:43 +0200 |
| commit | 199f830d19576c77a5ed8fec81c218258d73f1dd (patch) | |
| tree | 1a926e8db3733b5d675464f5a8b92b19ccdeb59e /target-ppc | |
| parent | f03328882f8008fc299d5f8ae33b9a80571fea3c (diff) | |
target-ppc: emulate lfiwax instruction
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
[agraf: fix tcg debug error]
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 19898185e6..228c695288 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -3300,6 +3300,26 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); /* lfs lfsu lfsux lfsx */ GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); +/* lfiwax */ +static void gen_lfiwax(DisasContext *ctx) +{ + TCGv EA; + TCGv t0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + t0 = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + gen_qemu_ld32u(ctx, t0, EA); + tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); + tcg_gen_ext32s_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); + tcg_temp_free(EA); + tcg_temp_free(t0); +} + /*** Floating-point store ***/ #define GEN_STF(name, stop, opc, type) \ static void glue(gen_, name)(DisasContext *ctx) \ @@ -9014,6 +9034,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type) GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) +GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), #undef GEN_STF #undef GEN_STUF |