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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-02-24 11:08:40 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-02-24 11:08:40 +0000 |
| commit | bf2fd13af3925f3a081fdeab8e8a1c8830431e46 (patch) | |
| tree | cec1c65f37248d2adf0ec1097cda2046ed84675a /target-mips/translate_init.c | |
| parent | cd2d5541271f1934345d8ca42f5fafff1744eee7 (diff) | |
| parent | 1ab2aea2489f34a05dabfe5bd91a76d89dd8c922 (diff) | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150213-2' into staging
MIPS patches 2015-02-13
Changes:
* bug fixes, cleanups and minor improvements
# gpg: Signature made Sat Feb 14 17:01:37 2015 GMT using RSA key ID 0B29DA6B
# gpg: Can't check signature: public key not found
* remotes/lalrae/tags/mips-20150213-2:
linux-user: correct stat structure in MIPS N32
target-mips: pass 0 instead of -1 as rs in microMIPS LUI instruction
target-mips: fix broken snapshotting
target-mips: use CP0EnLo_XI instead of magic number
target-mips: ll and lld cause AdEL exception for unaligned address
target-mips: fix detection of the end of the page during translation
target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processors
isa: remove isa_mem_base variable
gt64xxx: remove isa_mem_base usage
piix4: use PCI address space instead of system memory
mips: remove isa_mem_base usage
jazz: remove usage of isa_mem_base
jazz: do not explode QEMUMachineInitArgs structure
isa: add memory space parameter to isa_bus_new
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 1543f6c388..9e8433a919 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -474,7 +474,7 @@ static const mips_def_t mips_defs[] = .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, - .CP0_Status_rw_bitmask = 0x32F8FFFF, + .CP0_Status_rw_bitmask = 0x12F8FFFF, .SEGBITS = 42, .PABITS = 36, .insn_flags = CPU_MIPS64, @@ -575,7 +575,7 @@ static const mips_def_t mips_defs[] = .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, .CCRes = 2, - .CP0_Status_rw_bitmask = 0x32F8FFFF, + .CP0_Status_rw_bitmask = 0x12F8FFFF, .SEGBITS = 42, .PABITS = 36, .insn_flags = CPU_MIPS64R2, |