diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2011-01-14 20:39:19 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-14 20:39:19 +0100 |
| commit | 05ed9a991987fd2f117914f9b0f7157553837d1b (patch) | |
| tree | 64f6ff110553933307c90a6e6f92644cb6962e1c /target-arm | |
| parent | 98eac7cab4392ab28fa22265e27906f5b9c6c9da (diff) | |
target-arm: Set privileged bit in TB flags correctly for M profile
M profile ARM cores don't have a CPSR mode field. Set the bit in the
TB flags that indicates non-user mode correctly for these cores.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 07b92d67bb..5bcd53ac73 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -485,13 +485,19 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, target_ulong *cs_base, int *flags) { + int privmode; *pc = env->regs[15]; *cs_base = 0; *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT); - if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { + if (arm_feature(env, ARM_FEATURE_M)) { + privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); + } else { + privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; + } + if (privmode) { *flags |= ARM_TBFLAG_PRIV_MASK; } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |