diff options
| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2021-01-12 09:25:27 +0800 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-02-21 18:41:46 +0100 |
| commit | 6902759965852ae9fc099bb32af8f8dc4a098733 (patch) | |
| tree | 84686cad27f5cccb802aa3c51a1f25d0b01c9e11 /qemu-io-cmds.c | |
| parent | 283eae174e4944e4f26160aceeec444a13e52b03 (diff) | |
hw/intc/loongson_liointc: Fix per core ISR handling
Per core ISR is a set of 32-bit registers spaced by 8 bytes.
This patch fixed calculation of it's size and also added check
of alignment at reading & writing.
Fixes: Coverity CID 1438965 and CID 1438967
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Message-Id: <20210112012527.28927-1-jiaxun.yang@flygoat.com>
[PMD: Added Coverity CID]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'qemu-io-cmds.c')
0 files changed, 0 insertions, 0 deletions