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| author | Suraj Jitindar Singh <sjitindarsingh@gmail.com> | 2019-11-28 14:46:56 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:48 +1100 |
| commit | 32d0f0d8de37519bcaa720c41f0f693b66016f1b (patch) | |
| tree | d2c96d88ead142f7c9e126e2118e8eebb814c617 /python | |
| parent | 5cc7e69f6da5c52a0ac9f48ace40caf91fce807d (diff) | |
target/ppc: Add SPR ASDR
The Access Segment Descriptor Register (ASDR) provides information about
the storage element when taking a hypervisor storage interrupt. When
performing nested radix address translation, this is normally the guest
real address. This register is present on POWER9 processors and later.
Implement the ADSR, note read and write access is limited to the
hypervisor.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions