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| author | Yongbok Kim <yongbok.kim@mips.com> | 2017-03-24 08:54:49 -0300 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-03 05:49:12 -0300 |
| commit | 59e7592756903de13cc4196630e82c4c43aa9f8c (patch) | |
| tree | a48a9978bbbd7116f355403b6bf19c7069593b31 /python/tests | |
| parent | 92ec7805190313c9e628f8fc4eb4f932c15247bd (diff) | |
target/mips: Migrate TLB MemoryMapID register
Include CP0 MemoryMapID register in migration state.
Fixes: 99029be1c28 ("target/mips: Add implementation of GINVT instruction")
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
Message-ID: <AM9PR09MB4851FB6034EDB7FA191BA47E84402@AM9PR09MB4851.eurprd09.prod.outlook.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'python/tests')
0 files changed, 0 insertions, 0 deletions