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| author | Nicholas Piggin <npiggin@gmail.com> | 2024-08-06 23:13:14 +1000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-11-04 09:08:32 +1000 |
| commit | c5747965afca017e27a475082126594e8306c766 (patch) | |
| tree | 6cfab986d4724b43a66273bbd01506240b04a9b7 /os-posix.c | |
| parent | 0324d236d2918c18a9ad4a1081b1083965a1433b (diff) | |
target/ppc: PMIs are level triggered
In Book-S / Power processors, the performance monitor interrupts are
driven by the MMCR0[PMAO] bit, which is level triggered and not cleared
by the interrupt.
Others may have different performance monitor architecture, but none of
those are implemented by QEMU.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'os-posix.c')
0 files changed, 0 insertions, 0 deletions