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authorLluís Vilanova <vilanova@ac.upc.edu>2016-02-01 19:38:42 +0100
committerRiku Voipio <riku.voipio@linaro.org>2016-02-23 21:25:09 +0200
commit460c579f3ddc71bcf34128d4b3d1e1debdd93f73 (patch)
tree2e06b867f1e5c67b30fce4700b18e7bd50616138 /linux-user/tilegx/target_syscall.h
parent5089c7ce82a49e6a97c5cf3db57a89bca8ed25d8 (diff)
build: [linux-user] Rename "syscall.h" to "target_syscall.h" in target directories
This fixes double-definitions in linux-user builds when using the UST tracing backend (which indirectly includes the system's "syscall.h"). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
Diffstat (limited to 'linux-user/tilegx/target_syscall.h')
-rw-r--r--linux-user/tilegx/target_syscall.h43
1 files changed, 43 insertions, 0 deletions
diff --git a/linux-user/tilegx/target_syscall.h b/linux-user/tilegx/target_syscall.h
new file mode 100644
index 0000000000..a938d4e90c
--- /dev/null
+++ b/linux-user/tilegx/target_syscall.h
@@ -0,0 +1,43 @@
+#ifndef TILEGX_SYSCALLS_H
+#define TILEGX_SYSCALLS_H
+
+#define UNAME_MACHINE "tilegx"
+#define UNAME_MINIMUM_RELEASE "3.19"
+
+#define MMAP_SHIFT TARGET_PAGE_BITS
+
+#define TILEGX_IS_ERRNO(ret) \
+ ((ret) > 0xfffffffffffff000ULL) /* errno is 0 -- 4096 */
+
+typedef uint64_t tilegx_reg_t;
+
+struct target_pt_regs {
+
+ union {
+ /* Saved main processor registers; 56..63 are special. */
+ tilegx_reg_t regs[56];
+ struct {
+ tilegx_reg_t __regs[53];
+ tilegx_reg_t tp; /* aliases regs[TREG_TP] */
+ tilegx_reg_t sp; /* aliases regs[TREG_SP] */
+ tilegx_reg_t lr; /* aliases regs[TREG_LR] */
+ };
+ };
+
+ /* Saved special registers. */
+ tilegx_reg_t pc; /* stored in EX_CONTEXT_K_0 */
+ tilegx_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
+ tilegx_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
+ tilegx_reg_t orig_r0; /* r0 at syscall entry, else zero */
+ tilegx_reg_t flags; /* flags (see below) */
+ tilegx_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */
+ tilegx_reg_t pad[2];
+};
+
+#define TARGET_MLOCKALL_MCL_CURRENT 1
+#define TARGET_MLOCKALL_MCL_FUTURE 2
+
+/* For faultnum */
+#define TARGET_INT_SWINT_1 14
+
+#endif