diff options
| author | Cédric Le Goater <clg@kaod.org> | 2019-06-30 22:45:53 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-07-02 09:43:58 +1000 |
| commit | 8256870ada9379abfd1f5b2c209ad01092dd0904 (patch) | |
| tree | 00fbeacc234b617d65aed76f0a3281e466228870 /linux-user/mips/cpu_loop.c | |
| parent | fe9a9d527da8ae939ee7eb32cb0045d2c3f75a11 (diff) | |
ppc/xive: Make the PIPR register readonly
When the hypervisor (KVM) dispatches a vCPU on a HW thread, it restores
its thread interrupt context. The Pending Interrupt Priority Register
(PIPR) is computed from the Interrupt Pending Buffer (IPB) and stores
should not be allowed to change its value.
Fixes: 207d9fe98510 ("ppc/xive: introduce the XIVE interrupt thread context")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190630204601.30574-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'linux-user/mips/cpu_loop.c')
0 files changed, 0 insertions, 0 deletions