diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2021-07-16 09:03:11 +0100 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2021-07-16 09:03:11 +0100 |
commit | 65388f404492daac86e02980d10ae84c694870b3 (patch) | |
tree | 9cf46148576e8c6f768dd33255cb209d37fdc564 /include | |
parent | bd306cfeeececee73ff2cdb3de1229ece72f3b28 (diff) | |
parent | b3d8aa20692b1baed299790f4a65d6b0cfb1a0bc (diff) |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210715' into staging
Fourth RISC-V PR for 6.1 release
- Code cleanups
- Documentation improvements
- Hypervisor extension improvements with hideleg and hedeleg
- sifive_u fixes
- OpenTitan register layout updates
- Fix coverity issue
# gpg: Signature made Thu 15 Jul 2021 08:14:00 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20210715:
hw/riscv/boot: Check the error of fdt_pack()
hw/riscv: opentitan: Add the flash alias
hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
char: ibex_uart: Update the register layout
hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
hw/riscv: sifive_u: Correct the CLINT timebase frequency
docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
target/riscv: hardwire bits in hideleg and hedeleg
docs/system: riscv: Add documentation for virt machine
docs/system: riscv: Fix CLINT name in the sifive_u doc
target/riscv: csr: Remove redundant check in fp csr read/write routines
target/riscv: pmp: Fix some typos
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/hw/riscv/opentitan.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 86cceef698..9f93bebdac 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -40,6 +40,7 @@ struct LowRISCIbexSoCState { MemoryRegion flash_mem; MemoryRegion rom; + MemoryRegion flash_alias; }; typedef struct OpenTitanState { @@ -54,6 +55,7 @@ enum { IBEX_DEV_ROM, IBEX_DEV_RAM, IBEX_DEV_FLASH, + IBEX_DEV_FLASH_VIRTUAL, IBEX_DEV_UART, IBEX_DEV_GPIO, IBEX_DEV_SPI, @@ -81,6 +83,7 @@ enum { IBEX_DEV_ALERT_HANDLER, IBEX_DEV_NMI_GEN, IBEX_DEV_OTBN, + IBEX_DEV_PERI, }; enum { |