diff options
| author | Bin Meng <bin.meng@windriver.com> | 2021-01-26 14:00:03 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-03-04 09:43:29 -0500 |
| commit | 722f1352b6c248ead94efd77ff5726aa0cba949b (patch) | |
| tree | 5b66ed3f4a7400037ebd9bcfb19f453867c95776 /include/hw/riscv | |
| parent | 145b299139da92fb1b1048b393865bc96597d6b9 (diff) | |
hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
This adds the QSPI2 controller to the SoC, and connects an SD
card to it. The generation of corresponding device tree source
fragment is also added.
Specify machine property `msel` to 11 to boot the same upstream
U-Boot SPL and payload image for the SiFive HiFive Unleashed board.
Note subsequent payload is stored in the SD card image.
$ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \
-bios u-boot-spl.bin -drive file=sdcard.img,if=sd
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 8824b7c031..de1464a2ce 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -47,6 +47,7 @@ typedef struct SiFiveUSoCState { SiFiveUOTPState otp; SiFivePDMAState dma; SiFiveSPIState spi0; + SiFiveSPIState spi2; CadenceGEMState gem; uint32_t serial; @@ -85,6 +86,7 @@ enum { SIFIVE_U_DEV_UART1, SIFIVE_U_DEV_GPIO, SIFIVE_U_DEV_QSPI0, + SIFIVE_U_DEV_QSPI2, SIFIVE_U_DEV_OTP, SIFIVE_U_DEV_DMC, SIFIVE_U_DEV_FLASH0, @@ -99,6 +101,7 @@ enum { SIFIVE_U_L2CC_IRQ2 = 3, SIFIVE_U_UART0_IRQ = 4, SIFIVE_U_UART1_IRQ = 5, + SIFIVE_U_QSPI2_IRQ = 6, SIFIVE_U_GPIO_IRQ0 = 7, SIFIVE_U_GPIO_IRQ1 = 8, SIFIVE_U_GPIO_IRQ2 = 9, |