diff options
| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2024-09-16 18:35:18 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2024-11-04 16:03:24 -0500 |
| commit | fa19fe4e3a61765ff60914ee00fc1e7a6a38dba9 (patch) | |
| tree | d4745879c1eed8b8a373ba0fa6225c8671e75668 /include/hw/pci-bridge | |
| parent | 14bd0f3865489d537a93b7c80617622473f224e4 (diff) | |
hw/pci-bridge/cxl-upstream: Add properties to control link speed and width
To establish performance characteristics of a CXL device when used via a
particular CXL topology (root ports, switches, end points) it is necessary
to set the appropriate link speed and width in the PCI Express capability
structure. Provide x-speed and x-link properties for this.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240916173518.1843023-7-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/pci-bridge')
| -rw-r--r-- | include/hw/pci-bridge/cxl_upstream_port.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bridge/cxl_upstream_port.h index 12635139f6..f208397ffe 100644 --- a/include/hw/pci-bridge/cxl_upstream_port.h +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -12,6 +12,10 @@ typedef struct CXLUpstreamPort { /*< public >*/ CXLComponentState cxl_cstate; CXLCCI swcci; + + PCIExpLinkSpeed speed; + PCIExpLinkWidth width; + DOECap doe_cdat; uint64_t sn; } CXLUpstreamPort; |