diff options
| author | Song Gao <gaosong@loongson.cn> | 2024-05-28 16:38:54 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2024-06-06 11:56:45 +0800 |
| commit | f2e61edb2946b0473ad634ed8ec401954ace5c5a (patch) | |
| tree | fc6c0d7f817b062dcaeccc473fbe15a07eafefe9 /hw | |
| parent | dc6f37eb957b2888fea78bda9da0cf0840dd795f (diff) | |
hw/loongarch/virt: Use MemTxAttrs interface for misc ops
Use MemTxAttrs interface read_with_attrs/write_with_attrs
for virt_iocsr_misc_ops.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20240528083855.1912757-3-gaosong@loongson.cn>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/loongarch/virt.c | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 2b5ae45939..0cef33a904 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -900,37 +900,49 @@ static void virt_firmware_init(LoongArchVirtMachineState *lvms) } -static void virt_iocsr_misc_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult virt_iocsr_misc_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { + return MEMTX_OK; } -static uint64_t virt_iocsr_misc_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, + uint64_t *data, + unsigned size, MemTxAttrs attrs) { - uint64_t ret; + uint64_t ret = 0; switch (addr) { case VERSION_REG: - return 0x11ULL; + ret = 0x11ULL; + break; case FEATURE_REG: ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); if (kvm_enabled()) { ret |= BIT(IOCSRF_VM); } - return ret; + break; case VENDOR_REG: - return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ + ret = 0x6e6f73676e6f6f4cULL; /* "Loongson" */ + break; case CPUNAME_REG: - return 0x303030354133ULL; /* "3A5000" */ + ret = 0x303030354133ULL; /* "3A5000" */ + break; case MISC_FUNC_REG: - return BIT_ULL(IOCSRM_EXTIOI_EN); + ret = BIT_ULL(IOCSRM_EXTIOI_EN); + break; + default: + g_assert_not_reached(); } - return 0ULL; + + *data = ret; + return MEMTX_OK; } static const MemoryRegionOps virt_iocsr_misc_ops = { - .read = virt_iocsr_misc_read, - .write = virt_iocsr_misc_write, + .read_with_attrs = virt_iocsr_misc_read, + .write_with_attrs = virt_iocsr_misc_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 4, |