diff options
| author | edgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-08 21:02:43 +0000 |
|---|---|---|
| committer | edgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-08 21:02:43 +0000 |
| commit | 78556820a4ef3f507ec7c26a86d5ac3889d93d1f (patch) | |
| tree | f86ef47bb672555e994b7323922064e3eeffa800 /hw | |
| parent | ca896ef389fc44c7a673d1bd2b94823e28da37a1 (diff) | |
CFI-0002 linux MTD compatibility.
* Add an extended table area.
* Clear buffer write timeouts to indicate that we dont support it.
* Correct device size.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4387 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/pflash_cfi02.c | 32 |
1 files changed, 25 insertions, 7 deletions
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index cb9b25093d..1daaac3d8e 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -608,8 +608,8 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, /* Command set (AMD/Fujitsu) */ pfl->cfi_table[0x13] = 0x02; pfl->cfi_table[0x14] = 0x00; - /* Primary extended table address (none) */ - pfl->cfi_table[0x15] = 0x00; + /* Primary extended table address */ + pfl->cfi_table[0x15] = 0x31; pfl->cfi_table[0x16] = 0x00; /* Alternate command set (none) */ pfl->cfi_table[0x17] = 0x00; @@ -627,22 +627,22 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, pfl->cfi_table[0x1E] = 0x00; /* Reserved */ pfl->cfi_table[0x1F] = 0x07; - /* Timeout for min size buffer write (16 µs) */ - pfl->cfi_table[0x20] = 0x04; + /* Timeout for min size buffer write (NA) */ + pfl->cfi_table[0x20] = 0x00; /* Typical timeout for block erase (512 ms) */ pfl->cfi_table[0x21] = 0x09; /* Typical timeout for full chip erase (4096 ms) */ pfl->cfi_table[0x22] = 0x0C; /* Reserved */ pfl->cfi_table[0x23] = 0x01; - /* Max timeout for buffer write */ - pfl->cfi_table[0x24] = 0x04; + /* Max timeout for buffer write (NA) */ + pfl->cfi_table[0x24] = 0x00; /* Max timeout for block erase */ pfl->cfi_table[0x25] = 0x0A; /* Max timeout for chip erase */ pfl->cfi_table[0x26] = 0x0D; /* Device size */ - pfl->cfi_table[0x27] = ctz32(chip_len) + 1; + pfl->cfi_table[0x27] = ctz32(chip_len); /* Flash device interface (8 & 16 bits) */ pfl->cfi_table[0x28] = 0x02; pfl->cfi_table[0x29] = 0x00; @@ -659,5 +659,23 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, pfl->cfi_table[0x2F] = sector_len >> 8; pfl->cfi_table[0x30] = sector_len >> 16; + /* Extended */ + pfl->cfi_table[0x31] = 'P'; + pfl->cfi_table[0x32] = 'R'; + pfl->cfi_table[0x33] = 'I'; + + pfl->cfi_table[0x34] = '1'; + pfl->cfi_table[0x35] = '0'; + + pfl->cfi_table[0x36] = 0x00; + pfl->cfi_table[0x37] = 0x00; + pfl->cfi_table[0x38] = 0x00; + pfl->cfi_table[0x39] = 0x00; + + pfl->cfi_table[0x3a] = 0x00; + + pfl->cfi_table[0x3b] = 0x00; + pfl->cfi_table[0x3c] = 0x00; + return pfl; } |