diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-09-03 19:00:04 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-10-21 13:19:02 +0200 |
| commit | 45e5dc43b3dab096bedf0d537e9b99ee169d0784 (patch) | |
| tree | c30f3fdff1aa67084b627df6fe4cc2c23e07ffa3 /hw | |
| parent | 6a9e5cc61c52af53c71ac24411324427650e6755 (diff) | |
hw/sd/sdhci: Resume pending DMA transfers on MMIO accesses
If we have pending DMA requests scheduled, process them first.
So far we don't need to implement a bottom half to process them.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20200903172806.489710-3-f4bug@amsat.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/sd/sdhci.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 61e469bd32..4db77decf8 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -948,11 +948,21 @@ sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) return true; } +static void sdhci_resume_pending_transfer(SDHCIState *s) +{ + timer_del(s->transfer_timer); + sdhci_data_transfer(s); +} + static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) { SDHCIState *s = (SDHCIState *)opaque; uint32_t ret = 0; + if (timer_pending(s->transfer_timer)) { + sdhci_resume_pending_transfer(s); + } + switch (offset & ~0x3) { case SDHC_SYSAD: ret = s->sdmasysad; @@ -1096,6 +1106,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) uint32_t value = val; value <<= shift; + if (timer_pending(s->transfer_timer)) { + sdhci_resume_pending_transfer(s); + } + switch (offset & ~0x3) { case SDHC_SYSAD: s->sdmasysad = (s->sdmasysad & mask) | value; |