diff options
author | Andreas Färber <afaerber@suse.de> | 2013-01-17 22:30:20 +0100 |
---|---|---|
committer | Andreas Färber <afaerber@suse.de> | 2013-03-12 10:35:55 +0100 |
commit | d8ed887bdcd29ce2e967f8b15a6a2b6dcaa11cd5 (patch) | |
tree | 57f8deccddd53e7aab5ca75d1d194da635a35790 /hw/sparc | |
parent | 259186a7d2f7184efc96ae99bc5658e6159f53ad (diff) |
exec: Pass CPUState to cpu_reset_interrupt()
Move it to qom/cpu.c to avoid build failures depending on include order
of cpu-qom.h and exec/cpu-all.h.
Change opaques of various ..._irq_handler() functions to the
appropriate CPU type to facilitate using cpu_reset_interrupt().
Fix Coding Style issues while at it (missing braces, indentation).
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'hw/sparc')
-rw-r--r-- | hw/sparc/leon3.c | 4 | ||||
-rw-r--r-- | hw/sparc/sun4m.c | 5 |
2 files changed, 7 insertions, 2 deletions
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index a9167e6f93..b1fbde0ff7 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -67,6 +67,7 @@ void leon3_irq_ack(void *irq_manager, int intno) static void leon3_set_pil_in(void *opaque, uint32_t pil_in) { CPUSPARCState *env = (CPUSPARCState *)opaque; + CPUState *cs; assert(env != NULL); @@ -89,9 +90,10 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_in) } } } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { + cs = CPU(sparc_env_get_cpu(env)); trace_leon3_reset_irq(env->interrupt_index & 15); env->interrupt_index = 0; - cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } } diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index a7e6966435..a1822f16f3 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -230,6 +230,8 @@ void sun4m_irq_info(Monitor *mon, const QDict *qdict) void cpu_check_irqs(CPUSPARCState *env) { + CPUState *cs; + if (env->pil_in && (env->interrupt_index == 0 || (env->interrupt_index & ~15) == TT_EXTINT)) { unsigned int i; @@ -247,9 +249,10 @@ void cpu_check_irqs(CPUSPARCState *env) } } } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { + cs = CPU(sparc_env_get_cpu(env)); trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); env->interrupt_index = 0; - cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } } |