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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2013-06-03 17:17:44 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-06-03 17:17:44 +0100
commitb0b7ae6259e96e775315357c813b74e85637bf32 (patch)
treeafc7d093052f987fbc4bb5d5cd7f035c89cead22 /hw/sd
parenta66418f6f181ca6ee04e77896674253ff83db45e (diff)
xilinx_spips: lqspi: Fix byte/misaligned access
The LQSPI bus attachment supports byte/halfword and misaligned accesses. Fixed. Refactored the LQSPI cache to be byte-wise instead of word wise accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 5ec47b13563ad2d22105a1f26186d7756718394b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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