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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-07-12 15:58:16 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-07-12 15:58:17 +0100 |
| commit | 552fda48e095c16a14c9d275b4fdc5c392c386cf (patch) | |
| tree | 1ede776f06b35d4817bce34b3744268607d64198 /hw/ppc | |
| parent | bd38ae26cea0d1d6a97f930248df149204c210a2 (diff) | |
| parent | 39d9919f4b4c3e7f230efd7d845439d6d732dc89 (diff) | |
Merge remote-tracking branch 'remotes/philmd/tags/mips-20210711' into staging
MIPS patches queue
- Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition
- Various Toshiba TX79 opcodes implemented
- Rewrite UHI errno_mips() using switch statement
- Few fixes and improvements in the SONIC model (dp8393x)
# gpg: Signature made Sun 11 Jul 2021 22:12:49 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/mips-20210711:
dp8393x: don't force 32-bit register access
dp8393x: Rewrite dp8393x_get() / dp8393x_put()
dp8393x: Store CAM registers as 16-bit
dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition
dp8393x: Replace address_space_rw(is_write=1) by address_space_write()
dp8393x: fix CAM descriptor entry index
target/mips: Rewrite UHI errno_mips() using switch statement
target/mips/tx79: Introduce SQ opcode (Store Quadword)
target/mips/tx79: Introduce LQ opcode (Load Quadword)
target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)
target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)
target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)
target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)
target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)
target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)
target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)
hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition
hw/pci-host: Rename Raven ASIC PCI bridge as raven.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ppc')
| -rw-r--r-- | hw/ppc/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 7fcafec60a..322a7eb031 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -85,7 +85,7 @@ config PREP imply PCI_DEVICES imply TEST_DEVICES select CS4231A - select PREP_PCI + select RAVEN_PCI select I82378 select LSI_SCSI_PCI select M48T59 |