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authorAurelien Jarno <aurelien@aurel32.net>2012-09-27 21:48:56 +0200
committerAurelien Jarno <aurelien@aurel32.net>2012-09-27 21:48:56 +0200
commit6f8fd2530e9a530f237240daf1c981fa5df7f978 (patch)
tree9f3710a6280bf4cc6ebca1433fab156a442846e3 /hw/pl190.c
parentd885bdd481fc1c11d3158cc1c4c68bffdb2c26fe (diff)
parent3dc3e7dd936f2e7f3e6dd4056f81c8961dc8201b (diff)
Merge branch 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: Versatile Express: Add modelling of NOR flash Versatile Express: Fix NOR flash 0 address and remove flash alias hw/armv7m_nvic: Correctly register GIC region when setting up NVIC pl190: fix read of VECTADDR
Diffstat (limited to 'hw/pl190.c')
-rw-r--r--hw/pl190.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/hw/pl190.c b/hw/pl190.c
index cb50afb9f4..7332f4dbae 100644
--- a/hw/pl190.c
+++ b/hw/pl190.c
@@ -117,12 +117,18 @@ static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
return s->protected;
case 12: /* VECTADDR */
/* Read vector address at the start of an ISR. Increases the
- current priority level to that of the current interrupt. */
- for (i = 0; i < s->priority; i++)
- {
- if ((s->level | s->soft_level) & s->prio_mask[i])
- break;
- }
+ * current priority level to that of the current interrupt.
+ *
+ * Since an enabled interrupt X at priority P causes prio_mask[Y]
+ * to have bit X set for all Y > P, this loop will stop with
+ * i == the priority of the highest priority set interrupt.
+ */
+ for (i = 0; i < s->priority; i++) {
+ if ((s->level | s->soft_level) & s->prio_mask[i + 1]) {
+ break;
+ }
+ }
+
/* Reading this value with no pending interrupts is undefined.
We return the default address. */
if (i == PL190_NUM_PRIO)