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authorAnthony Liguori <aliguori@us.ibm.com>2012-10-29 14:31:47 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2012-10-29 14:31:47 -0500
commit233926fafa6c4a0fb666e1469524d66dd3b47ddd (patch)
tree2dbe1506ee13fbc7d2d56b317f596114d0f849bb /hw/pci.h
parentb308c82cbda44e138ef990af64d44a5613c16092 (diff)
parent523a59f596a3e62f5a28eb171adba35e71310040 (diff)
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
virtio,pci infrastructure This includes infrastructure patches that don't do much by themselves but should help vfio and q35 make progress. Also included is rework of virtio-net to use iovec APIs for vector access - helpful to make it more secure and in preparation for a new feature that will allow arbitrary s/g layout for guests. Also included is a pci bridge bugfix by Avi. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> * mst/tags/for_anthony: (25 commits) pci: avoid destroying bridge address space windows in a transaction virtio-net: enable mrg buf header in tap on linux virtio-net: test peer header support at init time virtio-net: minor code simplification virtio-net: simplify rx code virtio-net: switch tx to safe iov functions virtio-net: first s/g is always at start of buf virtio-net: refactor receive_hdr virtio-net: use safe iov operations for rx virtio-net: avoid sg copy iov: add iov_cpy virtio-net: track host/guest header length pcie: Convert PCIExpressHost to use the QOM. pcie: pass pcie window size to pcie_host_mmcfg_update() pci: Add class 0xc05 as 'SMBus' pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle pci_ids: add intel 82801BA pci-to-pci bridge id pci: pci capability must be in PCI space pci: make each capability DWORD aligned qemu: enable PV EOI for qemu 1.3 ... Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/pci.h')
-rw-r--r--hw/pci.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/pci.h b/hw/pci.h
index 1f902f5b59..241c1d8905 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -318,6 +318,8 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque, int nirq);
int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
+/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
+int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque,
@@ -326,6 +328,7 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
uint8_t devfn_min, int nirq);
void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
+bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
void pci_device_set_intx_routing_notifier(PCIDevice *dev,
PCIINTxRoutingNotifier notifier);