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authorChen Qun <kuhn.chenqun@huawei.com>2020-03-13 20:32:42 +0800
committerPeter Maydell <peter.maydell@linaro.org>2020-03-17 11:23:14 +0000
commita510d0c1cd5e5cf267f9893368bb1c4ee7ccca19 (patch)
tree3569894ff0dc4fe774a69330ddfcc6defa4e18fa /hw/net/imx_fec.c
parent49cd55789bb17dba161fddf1817209999ce1d319 (diff)
hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
The current code causes clang static code analyzer generate warning: hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read value = value & 0x0000000f; ^ ~~~~~~~~~~~~~~~~~~ hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read value = value & 0x000000fd; ^ ~~~~~~~~~~~~~~~~~~ According to the definition of the function, the two “value” assignments should be written to registers. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Message-id: 20200313123242.13236-1-kuhn.chenqun@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/net/imx_fec.c')
-rw-r--r--hw/net/imx_fec.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 6a124a154a..5c145a8197 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -855,13 +855,15 @@ static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value)
break;
case ENET_TGSR:
/* implement clear timer flag */
- value = value & 0x0000000f;
+ s->regs[index] &= ~(value & 0x0000000f); /* all bits W1C */
break;
case ENET_TCSR0:
case ENET_TCSR1:
case ENET_TCSR2:
case ENET_TCSR3:
- value = value & 0x000000fd;
+ s->regs[index] &= ~(value & 0x00000080); /* W1C bits */
+ s->regs[index] &= ~0x0000007d; /* writable fields */
+ s->regs[index] |= (value & 0x0000007d);
break;
case ENET_TCCR0:
case ENET_TCCR1: