diff options
| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2023-06-01 14:13:29 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2023-06-10 10:19:24 -0300 |
| commit | f0fc1c29a8163ce383d3bcb3aac0964747d2d8b1 (patch) | |
| tree | 26007ae61b348975c0337427d24d9804ec6e762a /hw/intc/pnv_xive2.c | |
| parent | 32af01f83a763ccbba39c1cbc424e1b724d233df (diff) | |
pnv/xive2: Allow writes to the Physical Thread Enable registers
Fix what was probably a silly mistake and allow to write the Physical
Thread enable registers 0 and 1. Skiboot prefers to use the ENx_SET
variant so it went unnoticed, but there's no reason to discard a write
to the full register, it is Read-Write.
Fixes: da71b7e3ed45 ("ppc/pnv: Add a XIVE2 controller to the POWER10 chip")
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-4-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/intc/pnv_xive2.c')
| -rw-r--r-- | hw/intc/pnv_xive2.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index a75ff270ac..132f82a035 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1294,6 +1294,7 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, */ case TCTXT_EN0: /* Physical Thread Enable */ case TCTXT_EN1: /* Physical Thread Enable (fused core) */ + xive->tctxt_regs[reg] = val; break; case TCTXT_EN0_SET: |