diff options
author | Frederic Konrad <fkonrad@amd.com> | 2023-11-24 14:35:04 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2023-11-27 15:38:43 +0000 |
commit | a9bc470ec208bd27a82100abc9dccf1b69f41b45 (patch) | |
tree | 47b9a99a890212ffb4390e1386f77d8028766f40 /hw/dma/xlnx_csu_dma.c | |
parent | 90bb6d676489b5cc063858ece263e1586795803f (diff) |
hw/misc, hw/ssi: Fix some URLs for AMD / Xilinx models
It seems that the url changed a bit, and it triggers an error. Fix the URLs so
the documentation can be reached again.
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20231124143505.1493184-3-fkonrad@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/dma/xlnx_csu_dma.c')
-rw-r--r-- | hw/dma/xlnx_csu_dma.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index e89089821a..531013f35a 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -33,7 +33,7 @@ /* * Ref: UG1087 (v1.7) February 8, 2019 - * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html + * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers * CSUDMA Module section */ REG32(ADDR, 0x0) |