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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-03-14 14:28:47 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-03-14 14:28:47 +0000 |
| commit | caaf72fe471e1a1e4c7c2b93d29726267b49383b (patch) | |
| tree | 32086404f463cd404639a9561bcb2ec64e5ed471 /hw/display/vmware_vga.c | |
| parent | bf89cf14cd6b15e99d17eca62cbc16a22c485635 (diff) | |
| parent | 0d581506de803204c5a321100afa270573382932 (diff) | |
Merge tag 'pull-riscv-to-apply-20230314' of https://github.com/alistair23/qemu into staging
Seventh RISC-V PR for 8.0
* Fix slli_uw decoding
* Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
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* tag 'pull-riscv-to-apply-20230314' of https://github.com/alistair23/qemu:
Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
disas/riscv: Fix slli_uw decoding
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/display/vmware_vga.c')
0 files changed, 0 insertions, 0 deletions