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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2024-06-18 16:22:21 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2024-06-21 14:01:58 +0100 |
commit | 9b113a09ff34857d463c130faa873c7b6fc4a004 (patch) | |
tree | 04cf73d4107a855c699624eca5cc2c85a36aa8e0 /hw/cxl | |
parent | 7175a562f157d39725ab396e39c1e8e410d206b3 (diff) |
hw/arm/xilinx_zynq: Fix IRQ/FIQ routing
Fix the system bus interrupt line to CPU core assignment.
Fixes: ddcf58e044ce0 ("hw/arm/xilinx_zynq: Support up to two CPU cores")
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240610052906.4432-1-sebastian.huber@embedded-brains.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/cxl')
0 files changed, 0 insertions, 0 deletions