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author | Nikita Ostrenkov <n.ostrenkov@gmail.com> | 2023-11-12 16:56:58 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2023-11-13 16:31:41 +0000 |
commit | f6e8d1ef05a126de796ae03dd81e048e3ff48ff1 (patch) | |
tree | 713a3d3cdc5a19d4eb7bbe99c808b5d26f74a5b5 /hw/core | |
parent | 4d044472ab7666adf99d4daa0cc90b7502b90109 (diff) |
target/arm/tcg: enable PMU feature for Cortex-A8 and A9
According to the technical reference manual, the Cortex-A9
has a Perfomance Unit Monitor (PMU):
https://developer.arm.com/documentation/100511/0401/performance-monitoring-unit/about-the-performance-monitoring-unit
The Cortex-A8 does also.
We already already define the PMU registers when emulating the
Cortex-A8 and Cortex-A9, because we put them in v7_cp_reginfo[]
rather than guarding them behind ARM_FEATURE_PMU. So the only thing
that setting the feature bit changes is that the registers actually
do something.
Enable ARM_FEATURE_PMU for Cortex-A8 and Cortex-A9, to avoid
this anomaly.
(The A8 and A9 PMU predates the standardisation of ID_DFR0.PerfMon,
so the field there is 0, but the PMU is still present.)
Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Message-id: 20231112165658.2335-1-n.ostrenkov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message; also enable PMU for A8]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/core')
0 files changed, 0 insertions, 0 deletions