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| author | Shiva sagar Myana <Shivasagar.Myana@amd.com> | 2024-09-24 16:50:35 +0530 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-10-01 13:55:38 +0100 |
| commit | a8cc14435e675e86cba9afce8aa5e098b2e43ff4 (patch) | |
| tree | 710ddb8f743ea34a9f1d65b3607ecc2735a46285 /hw/core/irq.c | |
| parent | 67d762e716a7127ecc114e9708254316dd521911 (diff) | |
hw/ssi/xilinx_spips: Fix flash erase assert in dual parallel configuration
Ensure that the FIFO is checked for emptiness before popping data
from it. Previously, the code directly popped the data from the FIFO
without checking, which could cause an assertion failure:
../util/fifo8.c:67: fifo8_pop: Assertion `fifo->num > 0' failed.
Signed-off-by: Shiva sagar Myana <Shivasagar.Myana@amd.com>
Message-id: 20240924112035.1320865-1-Shivasagar.Myana@amd.com
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/core/irq.c')
0 files changed, 0 insertions, 0 deletions