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authorPeter Maydell <peter.maydell@linaro.org>2024-10-29 12:54:44 +0000
committerPeter Maydell <peter.maydell@linaro.org>2024-10-29 15:04:46 +0000
commit6128720af88eb9b5b3857f88785d32bc052049a7 (patch)
tree28fd51f69b03b0c6e0b11df3fb0128659dfddde9 /docs
parentf99e1d314d655561a0022902563eb5bffc260dc0 (diff)
docs/system/arm: Add placeholder doc for xlnx-zcu102 board
Add a placeholder doc for the xlnx-zcu102 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20241018141332.942844-6-peter.maydell@linaro.org
Diffstat (limited to 'docs')
-rw-r--r--docs/system/arm/xlnx-zcu102.rst19
-rw-r--r--docs/system/target-arm.rst1
2 files changed, 20 insertions, 0 deletions
diff --git a/docs/system/arm/xlnx-zcu102.rst b/docs/system/arm/xlnx-zcu102.rst
new file mode 100644
index 0000000000..534cd1dc88
--- /dev/null
+++ b/docs/system/arm/xlnx-zcu102.rst
@@ -0,0 +1,19 @@
+Xilinx ZynqMP ZCU102 (``xlnx-zcu102``)
+======================================
+
+The ``xlnx-zcu102`` board models the Xilinx ZynqMP ZCU102 board.
+This board has 4 Cortex-A53 CPUs and 2 Cortex-R5F CPUs.
+
+Machine-specific options
+""""""""""""""""""""""""
+
+The following machine-specific options are supported:
+
+secure
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
+ Arm Security Extensions (TrustZone). The default is ``off``.
+
+virtualization
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
+ Arm Virtualization Extensions. The default is ``off``.
+
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index a7f88c8f31..ace36d1b17 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -107,6 +107,7 @@ undocumented; you can get a complete list by running
arm/xenpvh
arm/xlnx-versal-virt
arm/xlnx-zynq
+ arm/xlnx-zcu102
Emulated CPU architecture support
=================================