diff options
| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2023-09-19 11:19:27 +0100 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-09-21 11:31:18 +0300 |
| commit | 6ee07cfbdfe4f2b1742a2143021f66e13bd738b0 (patch) | |
| tree | 91728403880055adb98a61ae945f557853aef108 /docs/system | |
| parent | 9da60248d1ca8e155f5c1279b4e55d70cad99341 (diff) | |
docs/cxl: Cleanout some more aarch64 examples.
These crossed with the previous fix to get rid of examples
using aarch64 for which support is not yet upstream.
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1892
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'docs/system')
| -rw-r--r-- | docs/system/devices/cxl.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index b742120657..6ab5f72473 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -313,7 +313,7 @@ A very simple setup with just one directly attached CXL Type 3 Persistent Memory A very simple setup with just one directly attached CXL Type 3 Volatile Memory device:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \ ... -object memory-backend-ram,id=vmem0,share=on,size=256M \ -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ @@ -323,7 +323,7 @@ A very simple setup with just one directly attached CXL Type 3 Volatile Memory d The same volatile setup may optionally include an LSA region:: - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \ + qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \ ... -object memory-backend-ram,id=vmem0,share=on,size=256M \ -object memory-backend-file,id=cxl-lsa0,share=on,mem-path=/tmp/lsa.raw,size=256M \ |