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authorDaniel Henrique Barboza <dbarboza@ventanamicro.com>2024-10-16 17:40:36 -0300
committerAlistair Francis <alistair.francis@wdc.com>2024-10-31 13:51:24 +1000
commit77cfbf5d08f8fbcc721b6309c560e4f48bdda8fd (patch)
tree34b8a9f46608aa2e62578945332978bcbf8c3072 /docs/system/riscv/virt.rst
parentd4f7804bac1bc67d49c78477baae36d070cd85d1 (diff)
docs/specs: add riscv-iommu
Add a simple guideline to use the existing RISC-V IOMMU support we just added. This doc will be updated once we add the riscv-iommu-sys device. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241016204038.649340-13-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'docs/system/riscv/virt.rst')
-rw-r--r--docs/system/riscv/virt.rst13
1 files changed, 13 insertions, 0 deletions
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index 9a06f95a34..8e9a2e4dda 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -84,6 +84,19 @@ none``, as in
Firmware images used for pflash must be exactly 32 MiB in size.
+riscv-iommu support
+-------------------
+
+The board has support for the riscv-iommu-pci device by using the following
+command line:
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...)
+
+Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU support
+works.
+
Machine-specific options
------------------------