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authorPeter Maydell <peter.maydell@linaro.org>2024-09-17 17:13:37 +0100
committerPeter Maydell <peter.maydell@linaro.org>2024-09-19 13:17:21 +0100
commit8676007eff04bb4e454bcdf92fab3f855bcc59b3 (patch)
tree4867b8a42fe637decb96eb413c8abcd8c9bfe5ac /docs/devel
parentc4d16d4168862735d746dd5d9e579cfc45c5e123 (diff)
target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1
The Neoverse-V1 TRM is a bit confused about the layout of the ID_AA64ISAR1_EL1 register, and so its table 3-6 has the wrong value for this ID register. Trust instead section 3.2.74's list of which fields are set. This means that we stop incorrectly reporting FEAT_XS as present, and now report the presence of FEAT_BF16. Cc: qemu-stable@nongnu.org Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240917161337.3012188-1-peter.maydell@linaro.org
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