diff options
| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-06-12 13:10:33 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-07-10 22:29:14 +1000 |
| commit | f6f72338d80ec6f15a6b18643797bc10901aadf3 (patch) | |
| tree | 177d8d276aa4dd93393fcce5b8268db4878b5762 /disas/riscv.c | |
| parent | c859a2424dbbae8f5ea64c0f8445981402cd8552 (diff) | |
disas/riscv: Add support for XVentanaCondOps
This patch adds XVentanaCondOps support to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'disas/riscv.c')
| -rw-r--r-- | disas/riscv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/disas/riscv.c b/disas/riscv.c index dc3bfb0123..c7bfd4ed32 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -22,6 +22,9 @@ #include "target/riscv/cpu_cfg.h" #include "disas/riscv.h" +/* Vendor extensions */ +#include "disas/riscv-xventana.h" + typedef enum { /* 0 is reserved for rv_op_illegal. */ rv_op_lui = 1, @@ -4708,6 +4711,7 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst, void (*decode_func)(rv_decode *, rv_isa); } decoders[] = { { always_true_p, rvi_opcode_data, decode_inst_opcode }, + { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, }; for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { |