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authorRahul Pathak <rpathak@ventanamicro.com>2022-08-24 20:22:55 +0530
committerAlistair Francis <alistair@alistair23.me>2022-09-27 07:04:38 +1000
commit513eb437aef7687ad1963d935ffb884fff3c4775 (patch)
tree824a85ca54a06bdfd2cfaf2067ca10e6f58fe8e7 /disas.c
parent0c2d4671916333e5b66fd923279fb6fb62315bed (diff)
target/riscv: Remove sideleg and sedeleg
sideleg and sedeleg csrs are not part of riscv isa spec anymore, these csrs were part of N extension which is removed from the riscv isa specification. These commits removed all traces of these csrs from riscv spec (https://github.com/riscv/riscv-isa-manual) - commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)") commit b6cade07034d ("Remove N extension chapter for now") Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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