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authorPaolo Bonzini <pbonzini@redhat.com>2014-12-11 19:08:14 +0100
committerPaolo Bonzini <pbonzini@redhat.com>2014-12-15 17:34:05 +0100
commit023c3a9707d0d9259a1e858cdf7804dd10973fca (patch)
tree9689ebaa5e2618469db9a0d66eee21159ecf06e0 /default-configs/sh4-softmmu.mak
parent0d931d706266d6ada3bf22d3afca1afdc8d12fa9 (diff)
serial: update LSR on enabling/disabling FIFOs
When the transmit FIFO is emptied or enabled, the transmitter hold register is empty. When it is disabled, it is also emptied and in addition the previous contents of the transmitter hold register are discarded. In either case, the THRE bit in LSR must be set and THRI raised. When the receive FIFO is emptied or enabled, the data ready and break bits must be cleared in LSR. Likewise when the receive FIFO is disabled. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'default-configs/sh4-softmmu.mak')
0 files changed, 0 insertions, 0 deletions