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authorAlistair Francis <alistair.francis@wdc.com>2020-04-23 11:30:50 -0700
committerAlistair Francis <alistair.francis@wdc.com>2020-06-03 09:11:51 -0700
commitfe0fe4735e798578097758781166cc221319b93d (patch)
treec0eaed6519b02f036f32535a9d3aa66f561c148f /default-configs/riscv32-softmmu.mak
parent36b80ad99f7ea4979a4c5fc6e4072619b405e3b0 (diff)
riscv: Initial commit of OpenTitan machine
This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'default-configs/riscv32-softmmu.mak')
-rw-r--r--default-configs/riscv32-softmmu.mak1
1 files changed, 1 insertions, 0 deletions
diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index 1ae077ed87..94a236c9c2 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -10,3 +10,4 @@ CONFIG_SPIKE=y
CONFIG_SIFIVE_E=y
CONFIG_SIFIVE_U=y
CONFIG_RISCV_VIRT=y
+CONFIG_OPENTITAN=y