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| author | Glenn Miles <milesg@linux.vnet.ibm.com> | 2024-09-13 11:16:53 -0500 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-11-04 09:14:39 +1000 |
| commit | f82fec6c1f3bf127eb46e811b0a529d83793381c (patch) | |
| tree | 2aaf0b4dd4add44a051e374c5415ece7f8f767e5 /cpu-target.c | |
| parent | cfe9a7f286f8db4316a25ac4471d91db8b387262 (diff) | |
ppc/xive2: Support "Pull Thread Context to Register" operation
Adds support for single byte read of offset 0x838 of the TIMA address
space. According to the XIVE2 Specification, this causes the hardware
to atomically:
1. Read the number of bytes requested (lbz or lhz are supported).
2. Reset the valid bit of the thread context.
3. Return the number of bytes requested in step 1 to a register.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'cpu-target.c')
0 files changed, 0 insertions, 0 deletions