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| author | Glenn Miles <milesg@linux.ibm.com> | 2024-09-13 11:16:57 -0500 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-11-04 09:14:48 +1000 |
| commit | 415313931917dc217f013a2ee977a059ee36bb3f (patch) | |
| tree | 97efdb5b7c28ac4a123fdf3024fbbb269191d4a1 /cpu-target.c | |
| parent | a9bb09678a7487609769f1965a04d3a774810bda (diff) | |
pnv/xive: Update PIPR when updating CPPR
Current code was updating the PIPR inside the xive_tctx_accept() function
instead of the xive_tctx_set_cppr function, which is where the HW would
have it updated.
Moved the update to the xive_tctx_set_cppr function which required
additional support for pool interrupts.
Fixes: cdd4de68edb6 ("ppc/xive: notify the CPU when the interrupt priority is more privileged")
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'cpu-target.c')
0 files changed, 0 insertions, 0 deletions