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| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-05 06:43:27 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-05 06:43:27 +0000 |
| commit | 6fa4cea9e8e904f7aac0c3d4f73a883c9e1e53bd (patch) | |
| tree | f9b4ad511745090b7f796be40c1ff8356f1eead5 /cpu-defs.h | |
| parent | 876d4b07832b3b4fd30510420631570b6b8c94ea (diff) | |
Infrastructure to support more than 2 MMU modes.
Add example for Alpha and PowerPC hypervisor mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2596 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'cpu-defs.h')
| -rw-r--r-- | cpu-defs.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/cpu-defs.h b/cpu-defs.h index 46cda20174..202eaee2e9 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -108,6 +108,15 @@ typedef struct CPUTLBEntry { target_phys_addr_t addend; } CPUTLBEntry; +/* Alpha has 4 different running levels */ +#if defined(TARGET_ALPHA) +#define NB_MMU_MODES 4 +#elif defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ +#define NB_MMU_MODES 3 +#else +#define NB_MMU_MODES 2 +#endif + #define CPU_COMMON \ struct TranslationBlock *current_tb; /* currently executing TB */ \ /* soft mmu support */ \ @@ -119,7 +128,7 @@ typedef struct CPUTLBEntry { target_ulong mem_write_vaddr; /* target virtual addr at which the \ memory was written */ \ /* 0 = kernel, 1 = user */ \ - CPUTLBEntry tlb_table[2][CPU_TLB_SIZE]; \ + CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ \ /* from this point: preserved by CPU reset */ \ |