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authorAlexander Graf <agraf@suse.de>2010-12-08 12:05:36 +0100
committerBlue Swirl <blauwirbel@gmail.com>2010-12-11 15:24:25 +0000
commitdd310534e3bf8045096654df41471fd7132887b2 (patch)
tree2511555233e06d50d07baad7ec8dfdccd17d7172 /cpu-common.h
parent85882c71a946796c0ddc87dc84cc6fcb05b375c7 (diff)
exec: introduce endianness swapped mmio
The way we're currently modeling mmio is too simplified. We assume that every device has the same endianness as the target CPU. In reality, most devices are little endian (all PCI and ISA ones I'm aware of). Some are big endian (special system devices) and a very little fraction is target native endian (fw_cfg). So instead of assuming every device to be native endianness, let's move to a model where the device tells us which endianness it's in. That way we can compile the devices only once and get rid of all the ugly swap will be done by the underlying layer. For the same of readability, this patch only introduces the helper framework but doesn't allow the registering code to set its endianness yet. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'cpu-common.h')
-rw-r--r--cpu-common.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/cpu-common.h b/cpu-common.h
index bb6b137e16..6d4a898ad1 100644
--- a/cpu-common.h
+++ b/cpu-common.h
@@ -20,6 +20,12 @@
#if !defined(CONFIG_USER_ONLY)
+enum device_endian {
+ DEVICE_NATIVE_ENDIAN,
+ DEVICE_BIG_ENDIAN,
+ DEVICE_LITTLE_ENDIAN,
+};
+
/* address in the RAM (different from a physical address) */
typedef unsigned long ram_addr_t;
@@ -55,7 +61,7 @@ ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write,
- void *opaque);
+ void *opaque, enum device_endian endian);
void cpu_unregister_io_memory(int table_address);
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,