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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-10-08 17:18:46 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-10-08 17:18:46 +0100 |
| commit | e64cf4d569f6461d6b9072e00d6e78d0ab8bd4a7 (patch) | |
| tree | efbcd66a45366ea73298f67075b07f7cd203c269 /accel/tcg/user-exec.c | |
| parent | a1d22c668a7662289b42624fe2aa92c9a23df1d2 (diff) | |
| parent | 62475e9d007d83db4d0a6ccebcda8914f392e9c9 (diff) | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20201008' into staging
Extend maximum gvec vector size
Fix i386 avx2 dupi
Fix mips host user-only write detection
Misc cleanups.
# gpg: Signature made Thu 08 Oct 2020 13:55:22 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20201008:
accel/tcg: Fix computing of is_write for MIPS
tcg: Remove TCG_TARGET_HAS_cmp_vec
tcg/optimize: Fold dup2_vec
tcg: Fix generation of dupi_vec for 32-bit host
tcg/i386: Fix dupi for avx2 32-bit hosts
tcg: Remove TCGOpDef.used
tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
tcg: Remove TCG_CT_REG
tcg: Move sorted_args into TCGArgConstraint.sort_index
tcg: Drop union from TCGArgConstraint
tcg: Adjust simd_desc size encoding
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'accel/tcg/user-exec.c')
| -rw-r--r-- | accel/tcg/user-exec.c | 43 |
1 files changed, 39 insertions, 4 deletions
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5c96819ded..4ebe25461a 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -702,16 +702,51 @@ int cpu_signal_handler(int host_signum, void *pinfo, #elif defined(__mips__) +#if defined(__misp16) || defined(__mips_micromips) +#error "Unsupported encoding" +#endif + int cpu_signal_handler(int host_signum, void *pinfo, void *puc) { siginfo_t *info = pinfo; ucontext_t *uc = puc; - greg_t pc = uc->uc_mcontext.pc; - int is_write; + uintptr_t pc = uc->uc_mcontext.pc; + uint32_t insn = *(uint32_t *)pc; + int is_write = 0; + + /* Detect all store instructions at program counter. */ + switch((insn >> 26) & 077) { + case 050: /* SB */ + case 051: /* SH */ + case 052: /* SWL */ + case 053: /* SW */ + case 054: /* SDL */ + case 055: /* SDR */ + case 056: /* SWR */ + case 070: /* SC */ + case 071: /* SWC1 */ + case 074: /* SCD */ + case 075: /* SDC1 */ + case 077: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 072: /* SWC2 */ + case 076: /* SDC2 */ +#endif + is_write = 1; + break; + case 023: /* COP1X */ + /* Required in all versions of MIPS64 since + MIPS64r1 and subsequent versions of MIPS32r2. */ + switch (insn & 077) { + case 010: /* SWXC1 */ + case 011: /* SDXC1 */ + case 015: /* SUXC1 */ + is_write = 1; + } + break; + } - /* XXX: compute is_write */ - is_write = 0; return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } |